Tom's Hardware50%
AMD’s new X100 chip lineup puts embedded Ryzen AI 'Strix Halo' chips into robots – APUs for physical AI bring Zen 5 CPU, RDNA 3.5 GPU cores to compete with Intel’s Panther Lake 48%
By Jake Roach24%
7/23/2026, 11:30:00 AM
Keywords: Amd, Strix Halo, Zen 5, Rdna 3 5, X100, Robotics, Physical AI, Apu, Cpu, Gpu, Intel Panther Lake
BS Summary: This article contains 26 faulty reasoning types, including Optimism Bias, Framing Effect, and Confirmation Bias, with Ambiguity (Equivocation) as the most egregious example at 20.4% saturation with 107 hits. Analysis detected 1,224 faulty-reasoning hits from 524 analyzed words, generating a BS Score of 48.9% and a BS Rank of 48% (11,543 of 21,887 articles). This article is better (less manipulative) than 52.70% of the article peer group.
AMD is bringing its Strix Halo APUs into the world of physical AI.
The new X100 series of processors come with similar specs as the various Ryzen AI Max models floating around in client devices, but they’re tailored for 24/7 operation, with a 10-year lifecycle in embedded applications like robotics.
There are three SKUs that align with the three original Strix Halo models (not the updated versions with 40 CUs).
The top-end X199 comes with 16 Zen 5 cores and 40 RDNA 3.5 CUs.
The X188 steps down to 12 cores and 32 CUs, while the X168 comes with eight cores and the same 32 CUs.
AMD hasn’t shared detailed specifications for each model, but the company says the range goes up to a 5.1 GHz boost clock and 128 GB of unified memory.
They also include an XDNA 2 NPU with up to 50 TOPS, a configurable TDP between 45W and 120W, and operating temperature between -40 degrees Celsius up to 105 degrees.
AMD’s range bites back at Intel, which launched a range of Panther Lake SoCs for physical AI at the beginning of the year.
Both make an argument for SoCs in robotics, reducing latency when the CPU, AI accelerator, and memory are fragmented across separate chips.
The X100 range is just physically larger than Panther Lake, packing much more silicon on the SoC for more powerful deployments.
AMD shared some benchmarks for the X100 Kria, as well, comparing it to Nvidia’s Thor T5000.
These benchmarks weren’t run internally at AMD.
They were commissioned by AMD and ran by Open Navigation and Mimix.
Critically, the benchmarks didn’t test an X100 Kria board, or at least, not in the form it will take once it’s inside a robot or AMD’s developer box.
Instead, AMD is comparing Nvidia’s Jetson AGX Thor developer kit to a GMKtech EVO-X2 AI mini PC with a Ryzen AI Max+ 395 “configured to reflect Ryzen AI Embedded X199 specifications.” Naturally, the thermal and power environment of these chips will heavily influence performance.
It’s not exactly an apples-to-apples comparison, in other words.
There’s some sort of proxy stand-in or extrapolation of data across all of the benchmarks here, so keep that in mind as we work through the rest of AMD’s X100 announcements.
AMD is continuing its attempt to siphon developers away from Nvidia’s CUDA platform for development, as well.
It’s HIPIFY tool converts CUDA code to AMD’s HIP C++ portable code, and the company claims it can now handle 70-80% of the “effort” of porting on its own.
AMD tested on a Ryzen AI Max+ 395, once again configured to match the X199, and it ported 15 CUDA applications, comprising 1,199 lines of code, to arrive at that 70% to 80% range.
X100 Kria lives at the “brain” of the robotics platform, but AMD envisions an end-to-end solution for humanoid-style robots with its Spartan UltraScale+, Zynq UltraScale+, and Versal AI Edge Gen 2 FPGAs and SoCs
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